tag: Side-Channel · 6 items
- Engineer — Learn: CacheTracer demonstrates that LLM API reseller chains are often multi-layer and opaque — prompts may traverse undisclosed intermediaries who can inspect or alter them. No patch exists; the takeaway is to audit which LLM API endpoints you use and prefer direct provider access or contractually disclosed routing for sensitive workloads.
- SOC/IR — Skip
- Leader — Plan: This research surfaces a concrete vendor-risk gap: LLM API resellers may introduce undisclosed intermediaries with access to prompt and response content, creating confidentiality exposure. Add LLM API supply chain transparency (direct vs. reseller routing, data-handling attestations) to your AI vendor risk review criteria this quarter.
- Engineer — Plan: If you process sensitive credentials or JWTs in Cloudflare Workers, audit whether those secrets could be exposed to co-tenant side-channel leakage; consider moving high-sensitivity auth operations off shared serverless platforms or reducing secret lifetimes in Workers.
- SOC/IR — Learn: Novel remote Spectre variant demonstrating cross-tenant memory leakage in shared serverless runtimes; no IOCs or detection surface exist yet, but the technique advances the threat model for cloud-hosted execution environments.
- Leader — Learn: Research confirms meaningful cross-tenant isolation risks in shared serverless platforms; useful context for vendor risk conversations with Cloudflare and for evaluating where sensitive auth tokens are processed in your stack.
- Engineer — Learn: No patch or mitigation is available yet; this research demonstrates that existing Spectre v2 defenses can be bypassed, which is worth tracking for Linux kernel hardening decisions when a fix lands.
- SOC/IR — Skip
- Leader — Skip
- Engineer — Learn: MIT CSAIL research shows a timing gap in branch-predictor sanitization can be re-poisoned by a local unprivileged process, defeating default Spectre v2 mitigations on AMD Zen 2 and Intel; no patch or workaround is available yet, but engineers running multi-tenant Linux workloads should track vendor microcode and kernel responses as they emerge.
- SOC/IR — Skip
- Leader — Skip
- Engineer — Learn: Relevant for teams designing or evaluating cryptographic hardware; Vogls enables pre-silicon DPA testing at RTL/gate level, which could inform security requirements for custom silicon or FPGA-based crypto implementations.
- SOC/IR — Skip
- Leader — Skip
- Engineer — Learn: Novel finding that 5G PDCCH scheduling metadata leaks enough temporal pattern to identify FL model architecture families, enabling targeted downstream attacks. No patch exists; worth factoring into FL-over-cellular deployment design (e.g., traffic shaping, scheduling obfuscation) before adopting this stack.
- SOC/IR — Skip
- Leader — Skip