tag: Hardware-Security · 4 items
- Engineer — Learn: Academic research showing that HPC-based Spectre detection signatures warp significantly with background noise, attack variants, and adversarial pacing across Intel/ARM/AMD — relevant if evaluating runtime hardware anomaly detection tools, but no change to running systems required today.
- SOC/IR — Learn: The finding that static ML models trained on HPC telemetry fail in real-world noise conditions is useful context for evaluating any HPC-based Spectre detection coverage in your stack, but the paper provides no IOCs, rules, or hunt queries to act on now.
- Leader — Skip
- Engineer — Learn: Relevant for teams designing or evaluating cryptographic hardware; Vogls enables pre-silicon DPA testing at RTL/gate level, which could inform security requirements for custom silicon or FPGA-based crypto implementations.
- SOC/IR — Skip
- Leader — Skip
- Engineer — Learn: Novel cross-level attack class that bridges electromagnetic/physical fault injection with algorithmic backdoors in embedded neural networks, bypassing input-space defenses. No immediate patch action — relevant if you design or deploy ML inference on embedded hardware, as it signals a new threat surface to consider during architecture review.
- SOC/IR — Skip
- Leader — Skip
- Engineer — Learn: Laser fault injection bypassing hardware security is a meaningful attack-class research finding, but Tangem cards are consumer crypto hardware — not enterprise infrastructure. Worth understanding fault-injection threat models if you design or evaluate hardware security modules.
- SOC/IR — Skip
- Leader — Skip